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PRELIMINARY DATA SHEET
MICRONAS
BSP 3505D Baseband Sound Processor
Edition Oct. 21, 1998 6251-481-1PD
MICRONAS
BSP 3505D
Contents Page 4 4 4 4 5 5 5 6 6 6 7 8 9 9 9 9 9 10 11 11 12 12 13 13 14 14 15 15 16 17 17 17 17 18 18 18 19 19 19 20 20 20 20 Section 1. 1.1. 1.2. 1.3. 2. 2.1. 2.1.1. 2.2. 2.3. 2.4. 3. 3.1. 3.2. 3.2.1. 3.2.2. 3.2.3. 3.2.4. 3.3. 4. 4.1. 4.2. 4.3. 4.4. 4.4.1. 4.4.2. 4.4.3. 4.4.4. 4.4.5. 4.4.6. 4.4.7. 4.4.8. 4.4.9. 4.4.10. 4.4.11. 4.4.12. 4.4.13. 4.4.14. 4.5. 4.5.1. 4.5.2. 4.5.3. 4.5.4. 4.5.5. Title Introduction BSP 3505D Integrated Functions Features of the DSP-Section Features of the Analog Section Architecture of the BSP 3505D Analog Section and SCART Switching Facilities Standby Mode BSP 3505DAudio Baseband Processing Clock and Crystal Specifications Digital Control Output Pins I2C Bus Interface: Device and Subaddresses Protocol Description Proposal for BSP 3505D I2C Telegrams Symbols Write Telegrams Read Telegrams Examples Start Up Sequence: Power Up and I2C-Controlling Programming the BSP 3505D Register `MODE_REG' DSP Write Registers: Table and Addresses DSP Read Registers: Table and Addresses DSP Write Registers: Functions and Values Volume Loudspeaker Channel Balance Loudspeaker Channel Bass Loudspeaker Channel Treble Loudspeaker Channel Loudness Loudspeaker Channel Spatial Effects Loudspeaker Channel Volume SCART1 Channel Source Modes Channel Matrix Modes SCART Prescale Definition of Digital Control Output Pins Definition of SCART-Switching Facilities Beeper Automatic Volume Correction (AVC) DSP Read Registers: Functions and Values Quasi-Peak Detector BSP Hardware Version Code BSP Major Revision Code BSP Product Code BSP ROM Version Code
PRELIMINARY DATA SHEET
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PRELIMINARY DATA SHEET
BSP 3505D
Contents, continued Page 21 21 23 26 30 31 31 32 34 37 40 40 Section 5. 5.1. 5.2. 5.3. 5.4. 5.5. 5.5.1. 5.5.2. 5.5.3. 6. 7. 8. Title Specifications Outline Dimensions Pin Connections and Short Descriptions Pin Configurations Pin Circuits Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions Characteristics Application Circuit Appendix A: BSP 3505D Version History Data Sheet History
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BSP 3505D
Baseband Sound Processor Release Notes: The hardware description in this document is valid for the BSP 3505D version A2. 1. Introduction The BSP 3505D is designed as a single-chip Baseband Sound Processor for applications in analog and digital TV sets, video recorders, and satellite receivers. The IC is produced in submicron CMOS technology, and is fully pin and software compatible to the MSP 34xx family. The BSP 3505D is available in a PLCC68, PSDIP64, PSDIP52, PQFP80, and in a PQFP44 package. Note: The BSP 3505D version has reduced control registers and less functional pins. The remaining registers are software compatible to the MSP 34xxD. The pinning is compatible to the MSP 34xxD. 1.1. BSP 3505D Integrated Functions - Stereo baseband input via integrated A/D converters - Two stereo D/A converters - AVC: Automatic Volume Correction - Bass, treble, volume, loudness processing - Full SCART in/out matrix without restrictions - spatial effect (pseudostereo / basewidth enlargement) - Digital control output pins D_CTR_OUT0/1 - Reduction of necessary controlling - Less external components
MONO IN 2 2
PRELIMINARY DATA SHEET
1.2. Features of the DSP-Section - flexible selection of audio sources to be processed - digital baseband processing: volume, bass, treble, loudness, and spatial effects - simple controlling of volume, bass, treble, loudness, and spatial effects 1.3. Features of the Analog Section - two selectable analog stereo audio baseband inputs (= two SCART inputs) input level: 2 V RMS, input impedance: 25 k - one selectable analog mono input: input level: 2 V RMS, input impedance: 15 k - stereo high-quality A/D converter, S/N-Ratio: 85 dB - 20 Hz to 20 kHz bandwidth for SCART-to-SCARTcopy facilities - loudspeaker: stereo four-fold oversampled D/A-converter output level per channel: max. 1.4 VRMS output resistance: max. 5 k S/N-ratio: 85 dB at maximum volume max. noise voltage in mute mode: 10 V (BW: 20 Hz ...16 kHz) - stereo four-fold oversampled D/A converter supplying a stereo SCART-output output level per channel: max. 2 V RMS, output resistance: max. 0.5 k, S/N-Ratio: 85 dB (20 Hz...16 kHz)
2 I2C 2 Loudspeaker OUT
SCART1 IN SCART2 IN
BSP 3505D
2 SCART OUT
Fig. 1-2: Main I/O Signals BSP 3505D
Tuner
SIF VIF
FM/AM Mono
Loudspeaker
SCART1 SCART Inputs SCART2
2
BSP 3505D
2
SCART1
SCART Output
2
Fig. 1-1: Typical BSP 3505D application 4 Micronas
PRELIMINARY DATA SHEET
BSP 3505D
SCART_IN SC1_IN_L/R
2. Architecture of the BSP 3505D Fig. 2-2 shows a simplified block diagram of the IC. Its architecture is split into two main functional blocks: 1. DSP (digital signal processing) section performing audio baseband processing 2. analog section containing two A/D-converters, four D/A-converters, and SCART-switching facilities. 2.1. Analog Section and SCART Switching Facilities The analog input and output sections include full matrix switching facilities, which are shown in Fig. 2-1. The switches are controlled by the ACB bits defined in the audio processing interface (see section 4. Programming the BSP 3505D). 2.1.1. Standby Mode If the BSP 3505D is switched off by first pulling STANDBYQ low, and then disconnecting the 5 V, but keeping the 8 V power supply (`Standby'-mode), the switches S1 and S2 (see Fig. 2-1) maintain their position and function. This facilitates the copying from selected SCART-inputs to SCART-output in the TV-set's standby mode. In case of power-on start or starting from standby, the IC switches automatically to the default configuration, shown in Fig. 2-1. This action takes place after the first I2C transmission into the DSP part. By transmitting the ACB register first, the individual default setting mode of the TV set can be defined.
SC2_IN_L/R
to Audio Baseband Processing (DSP_IN) A D SCARTL/R
MONO_IN
S1
intern. Signal Lines Pins SCART_OUT
from Audio Baseband Processing (DSP_OUT) SCART1_L/R D A
SC1_OUT_L/R
S2
Fig. 2-1: SCART-Switching Facilities (see 4.4.12.) positions show the default configuration after Power On Reset. Note: SCART_OUT is undefined after RESET!
XTAL_IN
XTAL_OUT
Clock
DSP
LOUDSPEAKER L LOUDSPEAKER R
D_CTR_OUT0/1
D/A D/A
DACM_L
Loudspeaker
DACM_R
Mono
MONO_IN
SC1_IN_L
A/D A/D
SCARTL SCARTR
SCART1_L SCART1_R
D/A D/A
SC1_OUT_L
SCART1
SC1_IN_R
SCART
SC1_OUT_R
SC2_IN_L
SCART2
SC2_IN_R
SCART Switching Facilities
Fig. 2-2: Architecture of the BSP 3505D Micronas 5
BSP 3505D
2.2. BSP 3505D Audio Baseband Processing All audio baseband functions are performed by digital signal processing (DSP). The DSP functions are grouped into three processing parts: input preprocessing, channel source selection, and channel postprocessing (see Fig. 2-3). The input preprocessing is intended to form a standardized signal level. All input and output signals can be processed simultaneously. 2.3. Clock and Crystal Specifications Remark on using the crystal: External capacitors at each crystal pin to ground are required. The higher the capacitors, the lower the clock frequency results. The nominal free running frequency should match the center of the tolerance range between 18.433 and 18.431 MHz as closely as possible. 2.4. Digital Control Output Pins The static level of two output pins of the BSP 3505D (D_CTR_OUT0/1) is switchable between HIGH and LOW by means of the I2C-bus. This enables the controlling of external hardware controlled switches or other devices via I2C-bus (see section 4.4.11.)
PRELIMINARY DATA SHEET
Analog Inputs
SCARTL SCARTR
SCART Prescale
Loudspeaker Channel Matrix
AVC
Bass Treble
Volume Loudness Balance
Loudspeaker L Loudspeaker Outputs Loudspeaker R
Channel Souce Select
Beeper
SCART1 Channel Matrix
Volume
SCART1_L SCART1_R
SCART Output
Quasi peak readout L Quasi-Peak Detector SCART Internal signal lines (see Fig. 2-1) Quasi peak readout R
Fig. 2-3: Audio Baseband Processing (DSP-Firmware) 6 Micronas
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BSP 3505D
Due to the internal architecture of the BSP 3505D the IC cannot react immediately to an I2C request. The typical response time is about 0.3 ms for the DSP processor part. If the receiver (BSP) can't receive another complete byte of data until it has performed some other function; for example, servicing an internal interrupt, it can hold the clock line I2C_CL LOW to force the transmitter into a wait state. The positions within a transmission where this may happen are indicated by 'Wait' in section 3.1. The maximum Wait-period of the BSP during normal operation mode is less than 1 ms. I2C-Bus conditions caused by BSP hardware problems: In case of any internal error, the BSPs wait-period is extended to 1.8 ms. Afterwards, the BSP does not acknowledge (NAK) the device address. The data line will be left HIGH by the BSP and the clock line will be released. The master can then generate a STOP condition to abort the transfer. By means of NAK, the master is able to recognize the error state and to reset the IC via I2C-Bus. While transmitting the reset protocol (s. 5.2.4.) to `CONTROL', the master must ignore the not acknowledge bits (NAK) of the BSP. A general timing diagram of the I2C Bus is shown in Fig. 3-2.
3. I2C Bus Interface: Device and Subaddresses As a slave receiver, the BSP 3505D can be controlled via I2C bus. Access to internal memory locations is achieved by subaddressing. The DSP processor part has its own subaddressing register bank. In order to allow for more BSP or MSP ICs to be connected to the control bus, an ADR_SEL pin has been implemented. With ADR_SEL pulled to high, low, or left open, the BSP 3505D responds to changed device addresses. Thus, three identical devices can be selected. By means of the RESET bit in the CONTROL register, all devices with the same device address are reset. The IC is selected by asserting a special device address in the address part of an I2C transmission. A device address pair is defined as a write address (80, 84, or 88hex) and a read address (81, 85, or 89hex). Writing is done by sending the device write address first, followed by the subaddress byte, two address bytes, and two data bytes. Reading is done by sending the device write address, followed by the subaddress byte and two address bytes. Without sending a stop condition, reading of the addressed data is completed by sending the device read address (81, 85, or 89hex) and reading two bytes of data. Refer to Fig. 3-1: I2C Bus Protocol and section 3.2. Proposal for BSP 3505D I2C Telegrams.
Table 3-1: I2C Bus Device Addresses ADR_SEL Mode BSP device address Write 80hex Low Read 81hex Write 84hex High Read 85hex Write 88hex Left Open Read 89hex
Table 3-2: I2C Bus Subaddresses Name CONTROL TEST WR_DSP RD_DSP Binary Value 0000 0000 0000 0001 0001 0010 0001 0011 Hex Value 00 01 12 13 Mode Write Write Write Write Function software reset only for internal use write address DSP read address DSP
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Table 3-3: Control Register (Subaddress: 00hex) Name CONTROL Subaddress 00hex MSB 1 : RESET 0 : normal 14 0 13..1 0
PRELIMINARY DATA SHEET
LSB 0
3.1. Protocol Description Write to DSP
S write device address Wait ACK sub-addr ACK addr-byte high ACK addr-byte low ACK data-byte high ACK data-byte low ACK P
Read from DSP
S write device address Wait ACK sub-addr ACK addr-byte high ACK addr-byte low ACK S read device address Wait ACK data-byte high
Write to Control or Test Registers
S write device address Wait ACK sub-addr ACK data-byte high ACK data-byte low ACK P
Note: S = P= ACK = NAK = Wait =
I2C-Bus Start Condition from master I2C-Bus Stop Condition from master Acknowledge-Bit: LOW on I2C_DA from slave (= BSP, gray) or master (= CCU, hatched) Not Acknowledge-Bit: HIGH on I2C_DA from master (= CCU, hatched) to indicate `End of Read' or from BSP indicating internal error state I2C-Clock line held low by the slave (= BSP) while interrupt is serviced (<1.8 ms)
I2C_DA S I2C_CL Fig. 3-1: I2C bus protocol (Data: MSB first)
1 0
P
(MSB first; data must be stable while clock is high)
8
CCC CCC CCC CCC CCC CCC
ACK data-byte low NAK P
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PRELIMINARY DATA SHEET
BSP 3505D
FI2C I2C_CL TI2C4 TI2C3
TI2C1 I2C_DA as input
TI2C5
TI2C6
TI2C2
TI2COL2 I2C_DA as output
TI2COL1
Fig. 3-2: I2C bus timing diagram
3.2. Proposal for BSP 3505D I2C Telegrams 3.2.1. Symbols daw dar < > aa dd write device address read device address Start Condition Stop Condition Address Byte Data Byte
3.2.2. Write Telegrams

write to CONTROL register write data into DSP
3.2.3. Read Telegrams

read data from DSP
3.2.4. Examples
<80 00 80 00> <80 00 00 00> <80 12 00 08 02 20>
RESET BSP statically clear RESET set loudspeaker channel source to SCART, stereo
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3.3. Start Up Sequence: Power Up and I2C-Controlling After power on or RESET (see Fig. 3-3), the IC is in an inactive state. The CCU has to transmit the required coefficient set for a given operation via the I2C bus. Initialization must start with the MODE Register. The reset pin should not be >0.45*DVSUP (see recommended conditions) before the 5 Volt digital power supply (DVSUP) and the analog power supply (AVSUP) are >4.75 Volt AND the BSP clock is running. (Delay: 0.5 ms typ, 2 ms max) This means, if the reset low-high edge starts with a delay of 2 ms after DVSUP and AVSUP >4,75 Volt, even under worst case conditions, the reset is ok.
PRELIMINARY DATA SHEET
DVSUP/V AVSUP/V 4.75
Oscillator
time / ms max. 2
RESETQ 0.45 * DVSUP
time / ms min. 2
time / ms Fig. 3-3: Power-up sequence
Note: The reset should not reach high level before the oscillator has started. This requires a reset delay of >2 ms
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BSP 3505D
4. Programming the BSP 3505D 4.1. Register `MODE_REG' The register `MODE_REG' contains the control bits determining the operation mode of the BSP 3505D; Table 4-1 explains all bit positions.
Table 4-1: Control word `MODE_REG': All bits are "0" after power-on-reset Register MODE_REG Bit [0] [1] [2] [3-4] [5] [6-9] [10-15] Protocol long Function not used DCTR_TRI not used not used not used not used not used Digital_Control_Output tristate Write Address (hex) 0083 Comment Function mode register Definition must be 0 0 : active 1 : tristate must be 1 must be 0 must be 1 must be 0 must be 0
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4.2. DSP Write Registers: Table and Addresses
PRELIMINARY DATA SHEET
Table 4-2: DSP Write Registers; Subaddress: 12hex; if necessary these registers are readable as well.
DSP Write Register Volume loudspeaker channel Volume / Clipping Mode loudspeaker Balance loudspeaker channel [L/R] Balance Mode loudspeaker Bass loudspeaker channel Treble loudspeaker channel Loudness loudspeaker channel Loudness Filter Characteristic Spatial effect strength loudspeaker ch. Spatial effect mode/customize Volume SCART1 channel Volume / Mode SCART1 channel Loudspeaker channel source Loudspeaker channel matrix SCART1 channel source SCART1 channel matrix 000Ahex 0008hex 0007hex 0005hex 0002hex 0003hex 0004hex 0001hex Address 0000hex High/ Low H L H L H H H L H L H L H L H L Adjustable Range, Operational Modes [+12 dB ... -114 dB, MUTE] 1/8 dB Steps / Reduce Vol., Tone, Comprom. [0..100 / 100 % and vv][-127..0 / 0 dB and vv] [Linear mode / logarithmic mode] [+12 dB ... -12 dB] [+12 dB ... -12 dB] [0 dB ... +17 dB] [NORMAL, SUPER_BASS] [-100%...OFF...+100%] [SBE, SBE+PSE] [00hex ... 7Fhex],[+12 dB ... -114 dB, MUTE] [Linear mode / logarithmic mode] [SCART] [SOUNDA, SOUNDB, STEREO, MONO] [SCART] [SOUNDA, SOUNDB, STEREO, MONO] [SCART] Reset Mode MUTE 00hex
100%/100%
linear mode 0 dB 0 dB 0 dB NORMAL OFF SBE+PSE 00hex linear mode FM/AM SOUNDA FM/AM SOUNDA FM /AM
EEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE E EE E EEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE E EE E
Quasi-peak detector source Quasi-peak detector matrix Prescale SCART 000Chex H L [SOUNDA, SOUNDB, STEREO, MONO] [00hex ... 7Fhex] Bits [15..0] [00hex ... 7Fhex]/[00hex ... 7Fhex] [off, on, decay time] SOUNDA 00hex 00hex 0/0 off 000Dhex 0013hex 0014hex 0029hex H ACB Register (SCART Switching Facilities) Beeper Automatic Volume Correction H/L H/L H
4.3. DSP Read Registers: Table and Addresses Table 4-3: DSP Read Registers; Subaddress: 13hex DSP Read Register Quasi peak readout left Quasi peak readout right Address 0019hex 001Ahex High/Low H&L H&L Output Range [00hex ... 7FFFhex] [00hex ... 7FFFhex] 16 bit two's complement 16 bit two's complement
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BSP 3505D
The BSP 3505D loudspeaker volume function is divided up in a digital and an analog section. With Fast Mute, volume is reduced to mute position by digital volume only. Analog volume is not changed. This reduces any audible DC plops. Going back from Fast Mute should be done to the volume step before Fast Mute was activated.
4.4. DSP Write Registers: Functions and Values Write registers are 16 bit wide, whereby the MSB is denoted bit [15]. Transmissions via I2C bus have to take place in 16-bit words. Some of the defined 16-bit words are divided into low [7..0] and high [15..8] byte, or in an other manner, thus holding two different control entities. All write registers are readable. Unused parts of the 16-bit registers must be zero. Addresses not given in this table must not be written at any time! 4.4.1. Volume Loudspeaker Channel Volume Loudspeaker +12 dB +11.875 dB +0.125 dB 0 dB -0.125 dB -113.875 dB -114 dB Mute Fast Mute 0000hex 0111 1111 0000 0111 1110 1110 [15..4]
Clipping Mode Loudspeaker Reduce Volume Reduce Tone Control 7F0hex 7EEhex Compromise Mode
0000hex 0000 RESET 0001 0010
[3..0] 0hex 1hex 2hex
0111 0011 0010 732hex 0111 0011 0000 730hex 0111 0010 1110 72Ehex
0000 0001 0010 012hex 0000 0001 0000 010hex 0000 0000 0000 000hex RESET 1111 1111 1110 FFEhex
If the clipping mode is set to "Reduce Volume", the following clipping procedure is used: To prevent severe clipping effects with bass or treble boosts, the internal volume is automatically limited to a level where, in combination with either bass or treble setting, the amplification does not exceed 12 dB. If the clipping mode is "Reduce Tone Control", the bass or treble value is reduced if amplification exceeds 12 dB. If the clipping mode is "Compromise Mode", the bass or treble value and volume are reduced half and half if amplification exceeds 12 dB.
The highest given positive 8-bit number (7Fhex) yields in a maximum possible gain of 12 dB. Decreasing the volume register by 1 LSB decreases the volume by 1 dB. Volume settings lower than the given minimum mute the output. With large scale input signals, positive volume settings may lead to signal clipping.
Example: Red. Volume Red. Tone Con. Compromise
Vol.: +6 dB 3 6 4.5
Bass: +9 dB 9 6 7.5
Treble: +5 dB 5 5 5
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4.4.2. Balance Loudspeaker Channel Positive balance settings reduce the left channel without affecting the right channel; negative settings reduce the right channel leaving the left channel unaffected. In linear mode, a step by 1 LSB decreases or increases the balance by about 0.8% (exact figure: 100/127). In logarithmic mode, a step by 1 LSB decreases or increases the balance by 1 dB.
PRELIMINARY DATA SHEET
4.4.3. Bass Loudspeaker Channel Bass Loudspeaker +20 dB +18 dB +16 dB +14 dB 0002hex 0111 1111 0111 1000 0111 0000 0110 1000 0110 0000 0101 1000 0000 1000 0000 0001 0000 0000 RESET 1111 1111 1111 1000 1010 1000 1010 0000 H 7Fhex 78hex 70hex 68hex 60hex 58hex 08hex 01hex 00hex FFhex F8hex A8hex A0hex
Balance Mode Loudspeaker linear logarithmic
0001hex 0000 RESET 0001
[3..0] 0hex 1hex
+12 dB +11 dB +1 dB +1/8 dB 0 dB
Linear Mode -1/8 dB Balance Loudspeaker Channel [L/R] Left muted, Right 100% Left 0.8%, Right 100% Left 99.2%, Right 100% Left 100%, Right 100% Left 100%, Right 99.2% Left 100%, Right 0.8% Left 100%, Right muted 0001hex 0111 1111 0111 1110 0000 0001 0000 0000 RESET 1111 1111 1000 0010 1000 0001 H -1 dB 7Fhex 7Ehex 01hex 00hex FFhex 82hex 81hex With positive bass settings, internal overflow may occur even with overall volume less than 0 dB. This will lead to a clipped output signal. Therefore, it is not recommended to set bass to a value that, in conjunction with volume, would result in an overall positive gain. -11 dB -12 dB
Logarithmic Mode Balance Loudspeaker Channel [L/R] Left -127 dB, Right 0 dB Left -126 dB, Right 0 dB Left -1 dB, Right 0 dB Left 0 dB, Right 0 dB Left 0 dB, Right -1 dB Left 0 dB, Right -127 dB Left 0 dB, Right -128 dB 0001hex 0111 1111 0111 1110 0000 0001 0000 0000 RESET 1111 1111 1000 0001 1000 0000 H 7Fhex 7Ehex 01hex 00hex FFhex 81hex 80hex
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PRELIMINARY DATA SHEET
BSP 3505D
4.4.5. Loudness Loudspeaker Channel H 78hex 70hex 08hex 01hex 00hex FFhex F8hex A8hex A0hex Mode Loudness Loudspeaker Normal (constant volume at 1 kHz) Super Bass (constant volume at 2 kHz) 0004hex 0000 0000 RESET 0000 0100 L 00hex 04hex Loudness Loudspeaker +17 dB +16 dB +1 dB 0 dB 0004hex 0100 0100 0100 0000 0000 0100 0000 0000 RESET H 44hex 40hex 04hex 00hex
4.4.4. Treble Loudspeaker Channel Treble Loudspeaker +15 dB +14 dB +1 dB +1/8 dB 0 dB -1/8 dB -1 dB -11 dB -12 dB 0003hex 0111 1000 0111 0000 0000 1000 0000 0001 0000 0000 RESET 1111 1111 1111 1000 1010 1000 1010 0000
With positive treble settings, internal overflow may occur even with overall volume less than 0 dB. This will lead to a clipped output signal. Therefore, it is not recommended to set treble to a value that, in conjunction with volume, would result in an overall positive gain.
Loudness increases the volume of low and high frequency signals, while keeping the amplitude of the 1 kHz reference frequency constant. The intended loudness has to be set according to the actual volume setting. Because loudness introduces gain, it is not recommended to set loudness to a value that, in conjunction with volume, would result in an overall positive gain. By means of `Mode Loudness', the corner frequency for bass amplification can be set to two different values. In Super Bass mode, the corner frequency is shifted up. The point of constant volume is shifted from 1 kHz to 2 kHz.
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4.4.6. Spatial Effects Loudspeaker Channel Spatial Effect Strength Loudspeaker Enlargement 100% Enlargement 50% Enlargement 1.5% Effect off Reduction 1.5% Reduction 50% Reduction 100% 0005hex 0111 1111 0011 1111 0000 0001 0000 0000 RESET 1111 1111 1100 0000 1000 0000 H 7Fhex 3Fhex 01hex 00hex FFhex C0hex 80hex
PRELIMINARY DATA SHEET
There are several spatial effect modes available: Mode A (low byte = 00hex) is compatible to the formerly used spatial effect. Here, the kind of spatial effect depends on the source mode. If the incoming signal is in mono mode, Pseudo Stereo Effect is active; for stereo signals, Pseudo Stereo Effect and Stereo Basewidth Enlargement is effective. The strength of the effect is controllable by the upper byte. A negative value reduces the stereo image. A rather strong spatial effect is recommended for small TV sets where loudspeaker spacing is rather close. For large screen TV sets, a more moderate spatial effect is recommended. In mode A, even in case of stereo input signals, Pseudo Stereo Effect is active, which reduces the center image. In Mode B, only Stereo Basewidth Enlargement is effective. For mono input signals, the Pseudo Stereo Effect has to be switched on. It is worth mentioning, that all spatial effects affect amplitude and phase response. With the lower 4 bits, the frequency response can be customized. A value of 0000bin yields a flat response for center signals (L = R) but a high pass function of L or R only signals. A value of 0110bin has a flat response for L or R only signals but a lowpass function for center signals. By using 1000bin, the frequency response is automatically adapted to the sound material by choosing an optimal high pass gain.
Spatial Effect Mode Loudspeaker Stereo Basewidth Enlargement (SBE) and Pseudo Stereo Effect (PSE). (Mode A) Stereo Basewidth Enlargement (SBE) only. (Mode B)
0005hex 0000 RESET 0000 0010
[7..4] 0hex 0hex 2hex
Spatial Effect Customize Coefficient Loudspeaker max high pass gain 2/3 high pass gain 1/3 high pass gain min high pass gain automatic
0005hex
[3..0]
0000 RESET 0010 0100 0110 1000
0hex 2hex 4hex 6hex 8hex
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PRELIMINARY DATA SHEET
BSP 3505D
4.4.8. Channel Source Modes 0007hex 0000 RESET 0001 [3..0] 0hex 1hex Loudspeaker Source SCART1 Source Quasi-Peak Detector Source NONE (MSP3410: FM) 0008hex 000Ahex 000Chex 0000 0000 RESET 0000 0001 0000 0010 H H H 00hex 01hex 02hex
4.4.7. Volume SCART1 Volume Mode SCART1 linear logarithmic
Linear Mode Volume SCART1 OFF 0 dB gain (digital full scale (FS) to 2 VRMS output) +6 dB gain (-6 dBFS to 2 VRMS output) 0007hex 0000 0000 RESET 0100 0000 H 00hex 40hex
NONE (MSP3410: NICAM) SCART
4.4.9. Channel Matrix Modes Loudspeaker Matrix 0008hex 000Ahex 000Chex 0000 0000 RESET 0001 0000 0010 0000 0011 0000 L L L 00hex 10hex 20hex 30hex
0111 1111
7Fhex
SCART1 Matrix Quasi-Peak Detector Matrix SOUNDA / LEFT
Logarithmic Mode Volume SCART1 +12 dB +11.875 dB +0.125 dB 0 dB -0.125 dB -113.875 dB -114 dB Mute 0007hex 0111 1111 0000 0111 1110 1110 [15..4] 7F0hex 7EEhex
SOUNDB / RIGHT STEREO MONO
0111 0011 0010 732hex 0111 0011 0000 730hex 0111 0010 1110 72Ehex 4.4.10. SCART Prescale Volume Prescale SCART OFF 0 dB gain (2 VRMS input to digital full scale) +14 dB gain (400 mVRMS input to digital full scale) 000Dhex 0000 0000 RESET 0001 1001 0111 1111 H 00hex 19hex 7Fhex
0000 0001 0010 012hex 0000 0001 0000 010hex 0000 0000 0000 000hex RESET
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4.4.11. Definition of Digital Control Output Pins ACB Register D_CTR_OUT0 low (RESET) high D_CTR_OUT1 low (RESET) high 0013hex x0 x1 [15..14] 4.4.13. Beeper Beeper Volume OFF
PRELIMINARY DATA SHEET
0014hex 0000 0000 RESET 0111 1111 0014hex 0000 0001 0100 0000 1111 1111
H 00hex 7Fhex L 01hex 40hex FFhex
Maximum Volume (full digital scale FDS) 0x 1x Beeper Frequency 16 Hz (lowest)
4.4.12. Definition of SCART-Switching Facilities ACB Register DSP IN Selection of Source: * SC1_IN_L/R MONO_IN SC2_IN_L/R Mute SC1_OUT_L/R Selection of Source: SC2_IN_L/R MONO_IN SCART1 via D/A SC1_IN_L/R Mute 0013hex [13..0]
1 kHz 4 kHz (highest)
xx xx xx xx
xx00 xx01 xx10 xx11
xx00 xx00 xx00 xx10
0000 0000 0000 0000
A squarewave beeper can be added to the loudspeaker channel. The addition point is just before volume adjustment.
xx xx xx xx xx
01xx 10xx 11xx 01xx 11xx
x0x0 x0x0 x0x0 x1x0 x1x0
0000 0000 0000 0000 0000
* = RESET position, which becomes active at the time of the first write transmission on the control bus to the audio processing part (DSP). By writing to the ACB register first, the RESET state can be redefined. Note: After RESET, SC1_OUT_L/R is undefined!
Note: If "MONO_IN" is selected at the DSP_IN selection, the channel matrix mode of the corresponding output channel(s) must be set to "sound A".
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PRELIMINARY DATA SHEET
BSP 3505D
To reset the internal variables, the AVC should be switched off and on during any channel or source change. For standard applications, the recommended decay time is 4 sec. Note: AVC should not be used in any Dolby Prologic mode, except PANORAMA, where no other than the loudspeaker output is active. 4.5. DSP Read Registers: Functions and Values 8hex 4hex 2hex 1hex All readable registers are 16-bit wide. Transmissions via I2C bus have to take place in 16-bit words. Single data entries are 8 bit. Some of the defined 16-bit words are divided into low and high byte, thus holding two different control entities. These registers are not writeable. 4.5.1. Quasi-Peak Detector Quasi-Peak Readout Left Quasi-Peak Readout Right Quasi peak readout 0019hex 001Ahex H+L H+L
4.4.14. Automatic Volume Correction (AVC) AVC AVC AVC AVC 8 sec 4 sec 2 sec 20 ms on/off off and Reset of int. variables on Decay Time (long) (middle) (short) (very short) 0029hex 0000 RESET 1000 0029hex 1000 0100 0010 0001 [15.12] 0hex 8hex [11..8]
Different sound sources fairly often do not have the same volume level. Advertisement during movies, as well, usually has a different (higher) volume level than the movie itself. The Automatic Volume Correction (AVC) solves this problem and equalizes the volume levels. The absolute value of the incoming signal is fed into a filter with 16 ms attack time and selectable decay time. The decay time must be adjusted as shown in the table above. This attack/decay filter block works similar to a peak hold function. The volume correction value with its quasi continuous step width is calculated using the attack/decay filter output. The Automatic Volume Correction works with an internal reference level of -18 dBFS. This means, input signals with a volume level of -18 dBFS will not be affected by the AVC. If the input signals vary in a range of -24 dB to 0 dB, the AVC compensates this. Example: A static input signal of 1 kHz on Scart has an output level as shown in the table below. Scart Input 0 dbr = 2 Vrms 0 dBr -6 dBr -12 dBr -18 dBr -24 dBr -30 dBr Volume Correction -18 dB -12 dB -6 dB -0 dB + 6 dB + 6 dB Main Output 0 dBr = 1.4 Vrms -18 dBr -18 dBr -18 dBr -18 dBr -18 dBr -24 dBr
[0hex ... 7FFFhex] values are 16 bit two's complement
The quasi peak readout register can be used to read out the quasi peak level of any input source, in order to adjust all inputs to the same normal listening level. The refresh rate is 32 kHz. The feature is based on a filter time constant: attack-time: 1.3 ms decay-time: 37 ms
Loudspeaker Volume = 73hex = 0 dBFS Scart Prescale = 20hex i.e. 2.0 Vrms = 0 dBFS
Micronas
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BSP 3505D
4.5.2. BSP Hardware Version Code Hardware Version Hardware Version BSP 3505D - A2 001Ehex [00hex ... FFhex] 01hex H
PRELIMINARY DATA SHEET
A change in the hardware version code defines hardware optimizations that may have influence on the chip's behavior. The readout of this register is identical to the hardware version code in the chip's imprint.
4.5.3. BSP Major Revision Code Major Revision BSP 3505D 001Ehex 04hex L
4.5.4. BSP Product Code Product BSP 3505D 001Fhex 05hex H
4.5.5. BSP ROM Version Code ROM Version Major software revision BSP 3505D - A2 001Fhex [00hex ... FFhex] 02hex L
A change in the ROM version code defines internal software optimizations, that may have influence on the chip's behavior, e.g. new features may have been included. While a software change is intended to create no compatibility problems, customers that want to use the new functions can identify new BSP 3505D versions according to this number.
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PRELIMINARY DATA SHEET
BSP 3505D
5. Specifications 5.1. Outline Dimensions
1.1 x 45 9 1 61 0.48 16 x 1.27 0.1 = 20.32 0.1 1.27 0.1 1.2 x 45 0.9
10 2 1.6 9 25.125 0.125
60
1.27 0.1 15 24.22 0.1 27 26 0.4 0.2 4 0.1 15.6 0.1 14 0.1 0.3 3.2 0.2 0.24 0.27 0.06 0...15
2 0.711
9 0.22 0.07
26 27 25.125 0.125 43
44 1.9 4.05 4.75 0.15
0.1
Fig. 5-1: 68-Pin Plastic Leaded Chip Carrier Package (PLCC68) Weight approximately 4.8 g Dimensions in mm
SPGS7004-3/5E
SPGS0016-4/3E
SPGS0015-1/2E
64 2.5
33
52
1
32 3.8 0.1
3
1
57.7 0.1 (1)
19.3 0.1 18 0.1
0.3
47 0.1
3.2 0.4
4.8 0.4
1.9
0.27 0.06 1.778 0.05 0.457 0.3 1 0.1 31 x 1.778 = 55.118 0.1 20.1 0.5 1 0.1 0.457 1.778 0.05 25 x 1.778 = 44.47 0.1
1.29
Fig. 5-2: 64-Pin Plastic Shrink Dual Inline Package (PSDIP64) Weight approximately 9.0 g Dimensions in mm
Fig. 5-3: 52-Pin Plastic Shrink Dual In Line Package (PSDIP52) Weight approximately 5.5 g Dimensions in mm
Micronas
16 x 1.27 0.1 = 20.32 0.1
23.4
24.22 0.1
21
BSP 3505D
PRELIMINARY DATA SHEET
23 x 0.8 = 18.4 0.17 0.03 64 65 1.8 17.2 10.3 9.8 16 8 14 41 40 1.8 15 x 0.8 = 12.0 8 0.8 0.8
5 25 1.28 2.70 3 0.2 0.1 20
80 1
24 23.2
Fig. 5-4: 80-Pin Plastic Quad Flat Package (PQFP80) Weight approximately 1.6 g Dimensions in mm
SPGS0025-1/1E
10 x 0.8 = 8 0.18 33 34 13.2 23 22 10 x 0.8 = 8 3.0 0.375 1.3 12 1 1.75 13.2 2.15 11 2.0 0.1 10 10 0.8 0.8
1.75
44
Fig. 5-5: 44-Pin Plastic Quad Flat Package (PQFP44) Weight approx. 0.4 g Dimensions in mm
SPGS0006-1/1E
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PRELIMINARY DATA SHEET
BSP 3505D
5.2. Pin Connections and Short Descriptions NC = not connected; leave vacant LV = if not used, leave vacant DVSS: if not used, connect to DVSS
Pin No. PLCC 68-pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 - - - PSDIP 64-pin 16 - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 - 1 64 63 62 61 60 59 58 57 - - - PSDIP 52-pin 14 - 13 12 11 10 9 8 7 - 6 5 4 3 - - - 2 1 52 51 50 49 48 47 46 - - - PQFP 80-pin 9 - 8 7 6 5 4 3 2 1 80 79 78 77 76 75 - 74 73 72 71 70 69 68 67 66 65 64 63 PQFP 44-pin - - - 17 16 15 14 13 12 - 11 10 9 8 - - - - 7 6 5 4 - 3 2 1 - - - TP NC TP TP TP TP TP I2C_DA I2C_CL NC STANDBYQ ADR_SEL D_CTR_OUT0 D_CTR_OUT1 NC NC NC NC TP XTAL_OUT XTAL_IN TESTEN NC TP TP AVSUP AVSUP NC NC IN IN OUT IN IN IN IN OUT OUT OUT IN OUT IN/OUT IN/OUT IN/OUT IN/OUT OUT Pin Name
X = obligatory; connect as described in circuit diagram AHVSS: connect to AHVSS
Type
Connection (if not used) sed)
Short Description
LV LV LV LV LV LV LV X X LV X X LV LV LV LV LV LV LV X X X LV LV LV X X LV LV
Test pin Not connected Test pin Test pin Test pin Test pin Test pin I2C data I2C clock Not connected Standby (low-active) I2C Bus address select Digital control output 0 Digital control output 1 Not connected Not connected Not connected Not connected Test pin Crystal oscillator Crystal oscillator Test pin Not connected Test pin Test pin Analog power supply +5 V Analog power supply +5 V Not connected Not connected
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BSP 3505D
PRELIMINARY DATA SHEET
Pin No. PLCC 68-pin 27 - 28 - 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 - - - 44 45 46 47 48 49 50 51 52 PSDIP 64-pin 56 - 55 - 54 53 52 51 50 49 48 47 46 45 44 43 - 42 41 - - - 40 39 38 37 36 35 34 33 - PSDIP 52-pin 45 - 44 - 43 42 41 - 40 39 - 38 37 - - - - 36 35 - - - 34 33 32 31 30 29 28 27 - PQFP 80-pin 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 PQFP 44-pin 44 - 43 - 42 41 40 39 38 37 - - - - - - - 36 35 - - - 34 33 32 31 30 29 28 - -
Pin Name
Type
Connection (if not used)
Short Description
AVSS AVSS MONO_IN NC VREFTOP SC1_IN_R SC1_IN_L ASG1 SC2_IN_R SC2_IN_L TP NC NC NC NC NC NC AGNDC AHVSS AHVSS NC NC CAPL_M AHVSUP NC SC1_OUT_L SC1_OUT_R VREF1 NC NC NC OUT OUT IN IN IN IN IN
X X LV LV X LV LV AHVSS LV LV LV LV LV LV LV LV LV X X X LV LV X X LV LV LV X LV LV LV
Analog ground Analog ground Mono input Not connected Reference voltage Scart input 1 in, right Scart input 1 in, left Analog shield ground 1 Scart input 2 in, right Scart input 2 in, left Test Pin Not connected Not connected Not connected Not connected Not connected Not connected Analog reference voltage high voltage part Analog ground Analog ground Not connected Not connected Volume capacitor MAIN Analog power supply 8.0 V Not connected Scart output 1, left Scart output 1, right Reference ground 1 high voltage part Not connected Not connected Not connected
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PRELIMINARY DATA SHEET
BSP 3505D
Pin No. PLCC 68-pin 53 54 55 56 57 58 59 60 - - 61 62 63 64 65 66 - - 67 - - 68 PSDIP 64-pin 32 31 30 29 28 27 26 25 - - 24 23 22 21 20 19 - - 18 - - 17 PSDIP 52-pin - 26 - 25 24 23 22 21 - - 20 - - 19 18 17 - - 16 - - 15 PQFP 80-pin 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PQFP 44-pin - - - 27 26 25 24 23 - - 22 - - 21 - - - 20 19 - - 18
Pin Name
Type
Connection (if not used)
Short Description
NC NC NC DACM_L DACM_R VREF2 NC NC NC NC RESETQ NC NC NC TP DVSS DVSS DVSS DVSUP DVSUP DVSUP TP OUT IN IN OUT OUT
LV LV LV LV LV X LV LV LV LV X LV LV LV LV X X X X X X LV
Not connected Not connected Not connected Loudspeaker out, left Loudspeaker out, right Reference ground 2 high voltage part Not connected Not connected Not connected Not connected Power-on-reset Not connected Not connected Not connected Test pin Digital ground Digital ground Digital ground Digital power supply +5 V Digital power supply +5 V Digital power supply +5 V Test pin
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BSP 3505D
5.3. Pin Configurations
TP NC TP TP TP TP TP I2C_DA I2C_CL TP DVSUP DVSS TP NC NC NC RESETQ
PRELIMINARY DATA SHEET
NC STANDBYQ ADR_SEL D_CTR_OUT0 D_CTR_OUT1 NC NC NC NC TP XTAL_OUT XTAL_IN TESTEN NC TP TP AVSUP
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53
NC NC VREF2 DACM_R DACM_L NC NC NC NC NC NC VREF1 SC1_OUT_R SC1_OUT_L NC AHVSUP CAPL_M
BSP 3505D
52 51 50 49 48 47 46 45 44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
AVSS MONO_IN VREFTOP SC1_IN_R SC1_IN_L ASG1 SC2_IN_R SC2_IN_L TP NC NC NC NC NC NC
AHVSS AGNDC
Fig. 5-6: 68-pin PLCC package
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PRELIMINARY DATA SHEET
BSP 3505D
NC NC NC D_CTR_OUT1 D_CTR_OUT0 ADR_SEL STANDBYQ NC I2C_CL I2C_DA TP TP TP TP TP TP TP DVSUP DVSS TP NC NC NC RESETQ NC NC VREF2 DACM_R DACM_L NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13
64 63 62 61 60 59 58 57 56 55 54 53 52
TP XTAL_OUT XTAL_IN TESTEN NC TP TP AVSUP AVSS MONO_IN VREFTOP SC1_IN_R SC1_IN_L ASG1 SC2_IN_R SC2_IN_L TP NC NC NC NC NC AGNDC AHVSS CAPL_M AHVSUP NC SC1_OUT_L SC1_OUT_R VREF1 NC NC
TP NC D_CTR_OUT1 D_CTR_OUT0 ADR_SEL STANDBYQ I2C_CL I2C_DA TP TP TP TP TP TP TP DVSUP DVSS TP NC RESETQ NC NC VREF2 DACM_R DACM_L NC
1 2 3 4 5 6 7 8 9 10
52 51 50 49 48 47 46 45 44 43
XTAL_OUT XTAL_IN TESTEN NC TP TP AVSUP AVSS MONO_IN VREFTOP SC1_IN_R SC1_IN_L SC2_IN_R SC2_IN_L NC NC AGNDC AHVSS CAPL_M AHVSUP NC SC1_OUT_L SC1_OUT_R VREF1 NC NC
BSP 3505D
11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
BSP 3505D
14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
Fig. 5-8: 52-pin PSDIP package
Fig. 5-7: 64-pin PSDIP package
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BSP 3505D
TP NC NC NC NC NC NC AGNDC AHVSS AHVSS NC NC
PRELIMINARY DATA SHEET
SC2_IN_L SC2_IN_R ASG1 SC1_IN_L SC1_IN_R VREFTOP NC MONO_IN AVSS AVSS NC NC
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 AVSUP AVSUP TP TP NC TESTEN XTAL_IN XTAL_OUT TP NC NC NC D_CTR_OUT1 D_CTR_OUT0 ADR_SEL STANDBYQ 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 40 39 38 37 36 35 34 CAPL_M AHVSUP NC SC1_OUT_L SC1_OUT_R VREF1 NC NC NC NC NC NC DACM_L DACM_R VREF2 NC
BSP 3505D
33 32 31 30 29 28 27 26 25
NC I2C_CL I2C_DA TP TP TP TP TP TP TP DVSUP DVSUP TP DVSS DVSS DVSS DVSUP NC NC NC NC RESETQ NC
NC
Fig. 5-9: 80-pin PQFP package
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PRELIMINARY DATA SHEET
BSP 3505D
NC VREF1 SC1_OUT_R SC1_OUT_L NC AHVSUP DACM_L DACM_R VREF2 NC NC
33 32 31 30 29 28 27 26 25 24 23 CAPL_M AHVSS AGNDC SC2_IN_L SC2_IN_R ASG1 SC1_IN_L SC1_IN_R VREFTOP MONO_IN AVSS 34 35 36 37 38 39 40 41 42 43 44 1 AVSUP TP TP TESTEN XTAL_IN XTAL_OUT TP 2 3 4 5 6 7 8 9 10 11 STANDBYQ ADR_SEL D_CTR_OUT0 D_CTR_OUT1 22 21 20 19 18 RESETQ NC DVSS DVSUP TP TP TP TP TP I2C_DA I2C_CL
BSP 3505D
17 16 15 14 13 12
Fig. 5-10: 44-pin PQFP package
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BSP 3505D
5.4. Pin Circuits (pin numbers refer to PLCC68 package)
PRELIMINARY DATA SHEET
40 k
N GND Fig. 5-11: Input/Output Pins 8 and 9 (I2C_DA, I2C_CL)
3.75 V
Fig. 5-17: Input Pins 30, 31, 33, and 34 (SC1-2_IN_L/R)
125 k
Fig. 5-12: Input Pins 11, 12, and 61 (STANDBYQ, ADR_SEL, RESETQ)
3.75 V
Fig. 5-18: Pin 42 (AGNDC) DVSUP P N GND Fig. 5-13: Output Pins 13, and 14 (D_CTR_OUT0/1) Fig. 5-19: Capacitor Pin 44 (CAPL_M)
0...2 V
P
40 pF 80 k
3-30 pF
500 k
N
300 3.75 V
3-30 pF
Fig. 5-14: Input/Output Pins 20 and 21 (XTALIN/OUT)
Fig. 5-20: Output Pins 47, 48 (SC1_OUT_L/R)
VREFTOP
2.6V
AHVSUP Fig. 5-15: Pin 29 (VREFTOP)
0...1.2 mA
3.3 k 24 k 3.75 V
Fig. 5-16: Input Pin 28 (MONO_IN) 30
Fig. 5-21: Output Pins 56, 57 (DACM_L/R)
Micronas
PRELIMINARY DATA SHEET
BSP 3505D
5.5. Electrical Characteristics 5.5.1. Absolute Maximum Ratings Symbol TA TS VSUP1 VSUP2 VSUP3 dVSUP23 PTOT Parameter Ambient Operating Temperature Storage Temperature First Supply Voltage Second Supply Voltage Third Supply Voltage Voltage between AVSUP and DVSUP Chip Power Dissipation PLCC68 without Heat Spreader PSDIP64 without Heat Spreader PSDIP52 without Heat Spreader PQFP44 without Heat Spreader Input Voltage, all Digital Inputs Input Current, all Digital Pins Input Voltage, all Analog Inputs Input Current, all Analog Inputs Output Current, all SCART Outputs Output Current, all Analog Outputs except SCART Outputs Output Current, other pins connected to capacitors - SCn_IN_s,3) MONO_IN SCn_IN_s,3) MONO_IN SC1_OUT_s DACM_s3) CAPL_M AGNDC Pin Name - - AHVSUP DVSUP AVSUP AVSUP, DVSUP AHVSUP, DVSUP, AVSUP Min. 0 -40 -0.3 -0.3 -0.3 -0.5 Max. 701) 125 9.0 6.0 6.0 0.5 Unit C C V V V V
1200 1300 1200 9601) -0.3 -20 -0.3 -5
4), 5) 4)
mW
VIdig IIdig VIana IIana IOana IOana ICana
1) 2) 3) 4) 5)
VSUP2+0.3 +20 VSUP1+0.3 +5
4), 5) 4)
V mA2) V mA2)
4)
4)
For PQFP44 package, max. ambient operating temperature is 65 C. positive value means current flowing into the circuit "n" means "1" or "2", "s" means "L" or "R" The Analog Outputs are short circuit proof with respect to First Supply Voltage and Ground. Total chip power dissipation must not exceed absolute maximum rating.
Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions/Characteristics" of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
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BSP 3505D
5.5.2. Recommended Operating Conditions at TA = 0 to 70 C (65 C for PQFP44) Symbol VSUP1 VSUP2 VSUP3 VREIL tREIL VDIGIL VDIGIH tSTBYQ1 Parameter First Supply Voltage Second Supply Voltage Third Supply Voltage RESET Input High-Low and LowHigh Transition Voltage RESET Low Time after DVSUP Stable and Oscillator Startup Digital Input Low Voltage Digital Input High Voltage STANDBYQ Setup Time before Turn-off of Second Supply Voltage STANDBYQ, ADR_SEL, ADR SEL TESTEN STANDBYQ, DVSUP Pin Name AHVSUP DVSUP AVSUP RESETQ Min. 7.6 4.75 4.75 0.45 5
PRELIMINARY DATA SHEET
Typ. 8.0 5.0 5.0
Max. 8.4 5.25 5.25 0.8
Unit V V V VSUP2 s
0.2 0.8 1
VSUP2 VSUP2 s
I2C-Bus Recommendations VI2CIL VI2CIH fI2C tI2C1 tI2C2 tI2C3 tI2C4 tI2C5 tI2C6 I2C-BUS Input Low Voltage I2C-BUS Input High Voltage I2C-BUS Frequency I2C START Condition Setup Time I2C STOP Condition Setup Time I2C-Clock Low Pulse Time I2C-Clock High Pulse Time I2C-Data Setup Time Before Rising Edge of Clock I2C-Data Hold Time after Falling Edge of Clock I2C_CL, I2C_DA I2C_CL, I2C DA C_DA 0.6 I2C_CL I2C_CL, C_DA I2C DA I2C_CL 120 120 500 500 55 55 1.0 0.3 VSUP2 VSUP2 MHz ns ns ns ns ns ns
Crystal Recommendations fP fTOL DTEM RR C0 Parallel Resonance Frequency at 12 pF Load Capacitance Accuracy of Adjustment Frequency Variation versus Temperature Series Resistance Shunt (Parallel) Capacitance -100 -50 8 6.2 18.432 +100 +50 25 7.0 MHz ppm ppm pF
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PRELIMINARY DATA SHEET
BSP 3505D
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Load Capacitance Recommendations CL External Load Capacitance1) XTAL_IN, XTAL_OUT PSDIP PLCC 1.5 3.3 pF pF
Amplitude Recommendation for Operation with External Clock Input (Cload after reset = 22 pF) VXCA External Clock Amplitude XTAL_IN 0.7 Vpp
Analog Input and Output Recommendations CAGNDC AGNDC-Filter-Capacitor Ceramic Capacitor in Parallel CinSC VinSC VinMONO RLSC CLSC CVMA CFMA DC-Decoupling Capacitor in front of SCART Inputs SCART Input Level Input Level, Mono Input SCART Load Resistance SCART Load Capacitance Main Volume Capacitor Main Filter Capacitor CAPL_M DACM_s2) -10% 10 1 +10% MONO_IN SC1_OUT_s2) 10 6.0 SCn_IN_s2) AGNDC -20% -20% -20% 3.3 100 330 +20% 2.0 2.0 F nF nF VRMS VRMS k nF F nF
Recommendations for Reference Voltage Pin CVREFTOP VREFTOP-Filter-Capacitor Ceramic Capacitor in Parallel
1)
VREFTOP
-20% -20%
10 100
F nF
External capacitors at each crystal pin to ground are required. The higher the capacitors, the lower the clock frequency results. The nominal free running frequency should match 18.432 MHz as closely as possible. Due to different layouts of customer PCBs, the matching capacitor size should be defined in the application. The suggested values (1.5 pF/3.3 pF) are figures based on experience with various PCB layouts. "n" means "1" or "2", "s" means "L" or "R"
2)
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BSP 3505D
5.5.3. Characteristics
PRELIMINARY DATA SHEET
at TA = 0 to 70 C (65 C for PQFP44), fCLOCK = 18.432 MHz, VSUP1 = 7.6 to 8.4 V, VSUP2 = 4.75 to 5.25 V for min./max. values at TA = 60 C, fCLOCK = 18.432 MHz, VSUP1 = 8 V, VSUP2 = 5 V for typical values, TJ = Junction Temperature MAIN (M) = Loudspeaker Channel, AUX (A) = Headphone Channel
Symbol fCLOCK DCLOCK tJITTER VxtalDC tStartup ISUP1A Parameter Clock Input Frequency Clock High to Low Ratio Clock Jitter (Verification not provided in Production test) DC-Voltage Oscillator Oscillator Startup Time at VDD Slew-rate of 1 V/1 s First Supply Current (active)
Analog Volume for Main and Aux at 0dB Analog Volume for Main and Aux at -30dB
Pin Name XTAL_IN
Min.
Typ. 18.432
Max.
Unit MHz
Test Conditions
45
55 50
% ps
2.5 XTAL_IN, XTAL_OUT AHVSUP 9.6 6.3 DVSUP AVSUP AHVSUP 86 15 3.5 17.1 11.2 95 25 5.6 24.6 16.1 102 35 7.7 0.4 2
V ms
mA mA mA mA mA STANDBYQ = low
ISUP2A ISUP3A ISUP1S
Second Supply Current (active) Third Supply Current (active) First Supply Current (standby mode) at Tj = 27 C I2C-Data Output Low Voltage I2C-Data Output High Current I2C-Data Output Hold Time after Falling Edge of Clock I2C-Data Output Setup Time before Rising Edge of Clock
VI2COL II2COH tI2COL1 tI2COL2
I2C_DA
0.4 1.0
V A ns
II2COL = 3 mA VI2COH = 5 V
I2C_DA, I2C_CL
15
100
ns
fI2C = 1 MHz
Analog Ground VAGNDC0 RoutAGN AGNDC Open Circuit Voltage AGNDC Output Resistance AGNDC 3.63 70 3.73 125 3.83 180 V k Rload 10 M 3 V VAGNDC 4 V
Analog Input Resistance RinSC RinMONO SCART Input Resistance from TA = 0 to 70 C MONO Input Resistance from TA = 0 to 70 C SCn_IN_s1) 25 40 58 k fsignal = 1 kHz, I = 0.05 mA fsignal = 1 kHz, I = 0.1 mA
MONO_IN
15
24
35
k
Audio Analog-to-Digital-Converter VAICL Effective Analog Input Clipping Level for Analog-to-DigitalConversion "s" means "L" or "R" SCn_IN_s,1) MONO_IN 2.00 2.25 VRMS fsignal = 1 kHz
1)
"n" means "1", or "2";
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PRELIMINARY DATA SHEET
BSP 3505D
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
SCART Outputs RoutSC SCART Output Resistance at Tj = 27 C from TA = 0 to 70 C Deviation of DC-Level at SCART Output from AGNDC Voltage Gain from Analog Input to SCART Output Frequency Response from Analog Input to SCART Output bandwidth: 0 to 20000 Hz Effective Signal Level at SCARTOutput during full-scale digital input signal from DSP SCn_IN_s1) MONO_IN SC1_OUT_s1) SC1_OUT_s1) 200 200 -70 330 460 500 +70 mV fsignal = 1 kHz, I = 0.1 mA
dVOUTSC ASCtoSC frSCtoSC
-1.0
+0.5
dB
fsignal = 1 kHz with resp. to 1 kHz
-0.5
+0.5
dB
VoutSC
SC1_OUT_s1)
1.8
1.9
2.0
VRMS
fsignal = 1 kHz
Main Outputs RoutMA Main Output Resistance at Tj = 27 C from TA = 0 to 70 C DC-Level at Main-Output for Analog Volume at 0 dB for Analog Volume at -30 dB Effective Signal Level at Main-Output during full-scale digital input signal from DSP for Analog Volume at 0 dB DACM_s1) 2.1 2.1 3.3 4.6 5.0 k k fsignal = 1 kHz, I = 0.1 mA
VoutDCMA
1.8
2.04 61 1.37
2.28
V mV VRMS fsignal = 1 kHz
VoutMA
1.23
1.51
Analog Performance SNR Signal-to-Noise Ratio from Analog Input to SCART Output MONO_IN, SCn_IN_s1) SC1_OUT_s1) 93 96 dB Input Level = -20 dB, fsig = 1 kHz, equally weighted 20 Hz ... 20 kHz
THD
Total Harmonic Distortion from Analog Input to SCART Output MONO_IN, SCn_IN_s1) SC1_OUT_s1) 0.01 0.03 % Input Level = -3 dBr, fsig = 1 kHz, equally weighted 20 Hz ... 20 kHz
1)
"n" means "1" or "2";
"s" means "L" or "R"
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BSP 3505D
PRELIMINARY DATA SHEET
Symbol XTALK
Parameter Crosstalk attenuation - PLCC68 - PSDIP64
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions Input Level = -3 dB, fsig = 1 kHz, unused analog inputs connected to ground by Z < 1 k equally weighted 20 Hz ... 20 kHz
between left and right channel within SCART Input/Output pair (LR, RL) SCn_IN1) SC1_OUT PLCC68 PSDIP64 80 80 dB dB
PSRR: rejection of noise on AHVSUP at 1 kHz AGNDC From Analog Input to SCART Output AGNDC MONO_IN, SCn_IN_s1) SC1_OUT_s1) VREFTOP 2.4 80 70 dB dB
DCVREFTOP
1)
DC voltage at VREFTOP "s" means "L" or "R"
2.6
2.7
V
"n" means "1" or "2";
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Micronas
PRELIMINARY DATA SHEET
BSP 3505D
6. Application Circuit
C s. section 5.5.2. 10 F + 3.3 F + 100 nF 100 nF 18.432 MHz + 10 F
+8.0 V
XTAL_OUT (63) 20
VREFTOP (54) 29
CAPL_M (40) 44
AGNDC (42) 42
XTAL_IN (62) 21
1 F 1 F
28 (55) MONO_IN 330 nF
DACM_L (29) 56 1 nF DACM_R (28) 57
MAIN
31 (52) SC1_IN_L 330 nF 30 (53) SC1_IN_R 330 nF AHVSS 32 (51) ASG1 34 (49) SC2_IN_L 330 nF 33 (50) SC2_IN_R 330 nF SC1_OUT_L (37) 47
100 22 F
+
BSP 3505D
SC1_OUT_R (36) 48
100 22 F
+
5V
11 (7) STANDBYQ D_CTR_OUT0 (5) 13 D_CTR_OUT1 (4) 14 12 (6) ADR_SEL
5V
DVSS DVSS 8 (10) I2C_DA 9 (9) I2C_CL
TESTEN (61) 22 AVSS
61 (24) RESETQ
45 (39) AHVSUP
67 (18) DVSUP
43 (41) AHVSS
26 (57) AVSUP
49 (35) VREF1
100 nF ResetQ (from CCU, see section.3.3.) + 10 F 100 nF AVSS 100 nF
5V
5V
8.0 V
Note: Pin numbers refer to the PLCC68 package, numbers in brackets refer to the PSDIP64 package.
Application Note: All ground pins should be connected to one low-resistive ground plane. All supply pins should be connected separately with short and low-resistive lines to the power supply. Decoupling capacitors from DVSUP to DVSS, AVSUP to AVSS, and AHVSUP to AHVSS are recommended as close as possible to these pins. Decoupling of DVSUP and DVSS is most important. We recommend using Micronas
more than one capacitor. By choosing different values, the frequency range of active decoupling can be extended. In our application boards we use: 220 pF, 470 pF, 1.5 nF, and 10 F. The capacitor with lowest value should be placed nearest to the DVSUP and DVSS pins. The ASG1 pin should be connected as closely as possible to the MSP to ground. If it is lead with the SC1 inputlines as shielding line, it should NOT be conneted to ground at the SCART connector. 37
58 (27) VREF2
66 (19) DVSS
27 (56) AVSS
BSP 3505D
PRELIMINARY DATA SHEET
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Micronas
PRELIMINARY DATA SHEET
BSP 3505D
Micronas
39
BSP 3505D
7. Appendix A: BSP 3505D Version History A2 First hardware release BSP 3505D 8. Data Sheet History
PRELIMINARY DATA SHEET
1. Preliminary Data Sheet: "BSP 3505D Baseband Sound Processor", Oct. 21, 1998, 6251-481-1PD. First release of the preliminary data sheet.
Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed in Germany Order No. 6251-481-1PD
All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH.
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Micronas

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